AMD Just Bought a Chip That Runs One AI Model Faster Than Anything Else — and Nothing Else, Ever

On Thursday, August 6, AMD said it had reached a definitive agreement to buy Taalas Inc., a three-year-old Toronto startup with an unusual product. Taalas does not build a faster processor for running AI models. It builds a chip that is the model — the weights cast into the transistors themselves, permanently, at the factory.

The performance numbers are the reason anyone is paying attention. The tradeoff behind them is the reason the deal is interesting.

The Memory Wall, in One Paragraph

When a GPU runs a language model, the weights do not live inside the compute engine. They sit in high-bandwidth memory beside it, and for every token generated the chip drags them across to the math units and back. The multiplications are cheap. The commute is not. On modern inference workloads the processor spends much of its life waiting on memory — the industry calls this the memory wall, and it is why an AI accelerator’s advertised FLOPS so rarely translate into tokens on a screen.

Taalas removes the commute by removing the memory. Its chips are model-specific integrated circuits, or MSICs: the weights are etched into a mask-ROM fabric inside the logic itself, with a separate SRAM region reserved for the parts that genuinely have to change during a session — the KV cache, and fine-tuning adapters. Nothing streams in from HBM, because there is nothing to stream. The company’s slogan for this is “the model is the computer.”

What HC1 Actually Did

Taalas has one test chip in the world, called HC1, fabricated on TSMC’s 6-nanometer process. Running Meta’s Llama 3.1 8B, it produced 16,960 tokens per second — and that figure is per user, not aggregate throughput split across a queue.

The comparisons are where you should slow down, because they come from the company and the baselines move. In February, Taalas put HC1 at 73 times an Nvidia H200 at one-tenth the power. Coverage of the same February results elsewhere framed it as roughly 48 times faster than Nvidia GPUs and 8.5 times faster than Cerebras accelerators. Those are not the same claim, and none of them is an independent benchmark. What is not in dispute is the direction and the rough order of magnitude: this is a large multiple, not a 20% improvement, and the power figure is arguably the more important half of it.

The Catch Is Absolute

A finished Taalas part runs the model it was built for. Not that model’s successor, not a different model of the same size, not a competitor’s model you would rather use next quarter. One model. The flexibility that makes a GPU worth its price — the fact that a data center can point the same rack at a thousand different workloads and re-point it tomorrow — is gone entirely.

Taalas’s answer is that re-spinning is cheaper than it sounds. Because the design borrows from structured-ASIC practice, only two of the chip’s hundred-plus mask layers change from one model to the next, and the company puts a new tape-out at roughly two months using its own tooling. That is genuinely fast for silicon. It is still not fast compared to changing a line in a config file.

Analysts covering the deal landed in roughly the same place. Forrester’s summary was blunt — “the biggest risk is inflexibility.” Others noted that enterprises would effectively be buying chip-and-model bundles, and that if the model ages out early, it strands the hardware with it. The consensus workloads are the boring, enormous, unchanging ones: fraud detection, customer service automation, industrial computer vision, network operations, embedded copilots. If your deployment shifts every six months chasing better checkpoints, etching one into silicon is a bad trade. If you are running one stable model at ten billion tokens a day, it starts to look like the only sane trade.

Scaling It Up Is the Open Question

HC1 handled an 8-billion-parameter model. The next chip, HC2, aims at around 20 billion. Frontier models are one to two orders of magnitude larger than that, and since the weights are physically in the die, you cannot solve the gap by adding memory — you add chips. Running a trillion-parameter model this way, using pipeline parallelism, would take somewhere in the region of 50 accelerators.

That is a lot of silicon, and it is also the honest version of the pitch: 50 model-specific chips can still be smaller and dramatically less power-hungry than the GPU fleet doing the same job, because none of them is paying the memory tax. Whether that holds at frontier scale is unproven. Nobody has built it.

Why AMD, and Why Now

AMD is explicit that this does not replace its GPU line. Taalas silicon is meant to sit beside Instinct accelerators, inside the Helios racks and next to the EPYC processors AMD already sells, addressed through the ROCm software stack. Vamsi Boppana, who runs AMD’s AI group, framed the goal as offering “the right compute solutions for every AI workload” — which is corporate phrasing for: general-purpose parts for the workloads that keep changing, fixed-function parts for the ones that do not.

It is also the fourth AI acquisition AMD has made in nine months, after MK1 in November 2025, Mext in June and the FastFlowLM team in July. Bajic, notably, is an AMD alumnus who left, ran Tenstorrent, founded Taalas, and now returns to lead the Toronto team inside AMD’s AI group. AMD is calling this a full acquisition rather than an acquihire.

The competitive context is unmissable. In December 2025, Nvidia paid roughly $20 billion to license Groq’s inference technology and hire its leadership — its largest deal on record — and unveiled the resulting language processing unit at GTC in March. Both companies have now concluded that the next phase of this market is not about training bigger models but about serving existing ones cheaply, and both have bought their way into non-GPU silicon to do it. AMD shares rose about 1.5% on the news.

What to Take From This

• The bottleneck moved, and the industry is following it. Two of the three largest AI chip companies spent real money in eight months on hardware that exists specifically to stop moving weights around. That is a statement about where the cost now sits.
• 16,960 tokens per second is a vendor number. It is on a test chip, on an 8B model, from February, compared against baselines that shift depending on who is telling it. Treat the order of magnitude as real and the precise multiple as marketing until someone independent runs it.
• Inflexibility is the product, not a bug they forgot to fix. Every bit of the speedup comes from the thing that makes the chip useless for anything else. There is no version of this that is both hardwired and general.
• This is a bet that models are slowing down. Model-specific silicon only pays off if the model you etch is still the one you want in two years. In 2023 that would have been an absurd wager. AMD evidently thinks 2027 is different.
• Nothing ships yet. The deal is expected to close in Q4 2026, pending regulators. HC2 is not out. Every claim above rests on one test chip.